As semiconductor devices become highly integrated, the width of gate lines has been reduced and copper interconnection processes have been used. When using a contact hole to connect a source/ drain area and a gate to an interconnection, high integration and high performance are typically achieved by using a borderless contact technology.
Additionally, the area occupied by each unit device in a semiconductor device has been decreasing, as has the area in which a contact is formed. Therefore, contact resistance is often increased and a contact process margin is not easily ensured.
A metal-silicide layer is generally applied to a contact part in order to compensate for the increase in contact resistance, and a Borderless Contact (BLC) is applied in order to ensure a contact process margin.
As the line width of semiconductor devices has become smaller, contacts for interconnection among unit transistor devices have often been formed using a BLC method in which the contacts are directly formed in a source area or a drain area of a transistor without separately providing areas to form the contacts. Accordingly, the size of a chip can be further reduced,
Since the borderless contact hole of a semiconductor device exists in both an active region and an isolation layer, the line width of the semiconductor device can be reduced.
However, if the isolation layer is partially over-etched when the borderless contact hole is formed, junction leakage current often occurs.
This leads to the contact area between the borderless contact hole and an active area being decreased, which leads to an increase in the contact resistance.
Additionally, in highly integrated semiconductor devices, borderless contact technology often interferes with a source/drain region and an isolation region. In particular, junction portions are frequently damaged when a contact hole is formed to make contact with a source/drain region.
Thus, there exists a need in the art for an improved method of forming a contact hole in a semiconductor device.